Intel, Toshiba and Samsung have said they will join forces to develop chip technologies that could more than halve semiconductor line widths to 10 nanometers by 2016, according to the Japanese Nikkei newspaper.

Samsung and Toshiba - the world's top two makers of NAND-type memory - together with the world's largest chipmaker, Intel, intend to form a consortium and invite about 10 firms operating in semiconductor materials to join them, the Nikkei said.

Intel is currently working on a 32nm process, although the company has already detailed its roadmap to shrink that down to 22nm within two years. Intel and others have already produced SRAM using a 22nm process.

However, at this year's IDF, Intel general manager William Holt said chip making was getting more complicated the smaller the manufacturing process went, which may explain the need for co-operation in the industry.

Japan's Ministry of Economy, Trade and Industry was tipped to provide $61.21 million of the $123 million in initial funds for the R&D efforts, with the rest expected to come from the members of the consortium, the paper said.

Toshiba and Samsung plan to use the technologies to make 10 nanometer-class NAND flash memory and other chips, while Intel will look to develop faster microprocessors.


Read more: Chipmakers join forces to shrink manufacturing process | News | PC Pro http://www.pcpro.co.uk/news/362320/chip ... z13qMUb9U5

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I was thinking some time ago how individual companies could cope with the increasing costs of miniaturisation. This is probably a way of maintaining growth for Toshiba and Samsung. Though how long before they come up across even greater problems making the chips smaller.